Experimental analysis of computer system dependability
Fault-tolerant computer system design
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
IEEE Transactions on Parallel and Distributed Systems
An Integrated HW and SW Fault Injection Environment for Real-Time Systems
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Soft-Error Detection through Software Fault-Tolerance Techniques
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
An Approach to Concurrent Control Flow Checking
IEEE Transactions on Software Engineering
The N-Version Approach to Fault-Tolerant Software
IEEE Transactions on Software Engineering
System safety through automatic high-level code transformations: an experimental evaluation
Proceedings of the conference on Design, automation and test in Europe
SAFECOMP '01 Proceedings of the 20th International Conference on Computer Safety, Reliability and Security
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This paper deals with a method able to provide a mi-coprocessor-based system with safety capabilities by modifying the source code of the executed application, only. The method exploits a set of transformations, which can automatically be applied, thus greatly reducing the cost of designing a safe system, and increasing the confidence in its correctness. Fault Injection experiments have been performed on a sample application using two different systems based on CISC and RISC processors. Results demonstrate that the method effectiveness is rather independent on the adopted platform.