Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
IEEE Transactions on Parallel and Distributed Systems
Soft-Error Detection through Software Fault-Tolerance Techniques
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Soft-Error Detection Using Control Flow Assertions
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A New Hybrid Fault Detection Technique for Systems-on-a-Chip
IEEE Transactions on Computers
Software-Implemented Hardware Fault Tolerance
Software-Implemented Hardware Fault Tolerance
A Hybrid Approach to Fault Detection and Correction in SoCs
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
An Approach to Concurrent Control Flow Checking
IEEE Transactions on Software Engineering
The N-Version Approach to Fault-Tolerant Software
IEEE Transactions on Software Engineering
Guest editor's introduction: what is infrastructure IP?
IEEE Design & Test
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An increasing number of safety-critical applications are based on Systems-on-Chip (SoCs), thus pushing a new wave of research aiming at the development of suitable techniques for ensuring their reliability. Several fault tolerance techniques have been proposed to ensure their fault detection capabilities, based either on software-based or hardware-based techniques. In this paper, we propose an optimized version of a recently proposed hybrid approach, which is able to provide fault detection and correction capabilities with respect to transient faults for processor-based SoCs. The proposed solution exploits some modifications of the source code at high level and an Infrastructure IP (I-IP). The main advantage of the proposed method lies in the fact that it does not require any modification of the microprocessor core. Experimental results show that the proposed method can guarantee fault coverage mainly at the same cost of the original method providing fault detection, only.