Processor Control Flow Monitoring Using Signatured Instruction Streams
IEEE Transactions on Computers
Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa
IEEE Transactions on Computers
Concurrent Detection of Software and Hardware Data-Access Faults
IEEE Transactions on Computers
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
IEEE Transactions on Parallel and Distributed Systems
Stress-Based and Path-Based Fault Injection
IEEE Transactions on Computers
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
Concurrent Error Detection Using Watchdog Processors-A Survey
IEEE Transactions on Computers
Concurrent Process Monitoring with No Reference Signatures
IEEE Transactions on Computers
Hierarchical Checking of Multiprocessors Using Watchdog Processors
EDCC-1 Proceedings of the First European Dependable Computing Conference on Dependable Computing
Can Concurrent Checkers Help BIST?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Control-Flow Checking via Regular Expressions
ATS '01 Proceedings of the 10th Asian Test Symposium
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Datapath error detection with no detection latency for high-performance microprocessors
WSEAS Transactions on Computers
Evaluation and analysis of an on-line error detection monitoring technique
Computers and Electrical Engineering
| Hi-index | 14.98 |
In this paper, we present a new concurrent error-detection scheme by hybrid signature to the online detection of program memory and control flow errors caused by transient and intermittent faults. The proposed hybrid signature-monitoring technique combines the vertical signature with the horizontal signature schemes. We first develop a new vertical signature based on linear additive code whose signature length could be easily adjusted. The attribute of adjustable length in vertical signature offers the feasibility to integrate the vertical signature, horizontal signature, and length of block into a single signature word. The horizontal signature mechanism can compensate for the coverage degradation due to the reduction of vertical signature length and significantly decrease the error-detection latency as well. The extensive block-based bit-error simulation and hardware-based simulated fault injection experiment are conducted to validate the effectiveness of the proposed technique. Compared to the continuous signature monitoring (CSM) scheme, there are several notable enhancements accomplished in our work. One is the fault model used in our work is more realistic than the model employed in CSM. Another is the hardware-based experiments are performed so as to measure the design parameters more accurately. The final one is our scheme does not require being equipped with SEC-DED code in program memory in order to achieve the horizontal signatures if instruction bit correction is not an essential demand; as a result, our scheme is more flexible than CSM.