A self-checking generalized prediction checker and its use for built-in testing
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A New Design Method for Self-Checking Unidirectional Combinational Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A linear code-preserving signature analyzer COPMISR
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring
IEEE Transactions on Computers
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
| Hi-index | 14.98 |
Concurrent checkers are commonly used in computer systems to detect computational errors on-line, which enhances reliability. Using the coding theory framework developed earlier by the authors, it is shown in the following that concurrent checkers, already available within the circuit, can be utilized very effectively during off-line testing. Specifically, test time as well as fault escape probability can both be reduced simultaneously. The proposed combined scheme can be implemented with simple modification of existing hardware. Also shown is a novel use of BIST hardware for concurrent checking. Specifically proposed is a novel, dual use of concurrent checkers and built-in self-test hardware, yielding mutual advantage