Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks
IEEE Transactions on Computers
Can Concurrent Checkers Help BIST?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Logic Synthesis for Concurrent Error Detection
Logic Synthesis for Concurrent Error Detection
On Totally Self-Checking Checkers for Separable Codes
IEEE Transactions on Computers
Self-exercising checkers for unified built-in self-test (UBIST)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper for an arbitrary linear separable code the concept of a COde Preserving Multi-Input Signature Register COPMISR is introduced. For a code with k control bits 2/sup k2/ different COPMISR's can be designed. The optimum COPMISR with a minimum number of XOR-gates can be chosen from this large set. By different examples it is shown how the newly introduced COPMISR can be simultaneously utilized for concurrent checking, testing and localization of an eventually erroneous component of the monitored system. Since parity codes, group-parity codes, duplication codes and Hamming codes are special linear separable codes the concept of the COPMISR has a wide range of applications in different areas of on-line error detection and BIST.