A microcoded RISC

Authors:
D. K. DuBose;D. K. Fotakis;D. Tabak
Affiliations:
Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA;Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA;Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA
Venue:
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
Year:
1986

Citing 3
Cited 1

Reduced instruction set computer architectures for VLSI

Reduced instruction set computer architectures for VLSI
Reduced instruction set computers

Communications of the ACM - Special section on computer architecture
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A microprogrammed interpreter for concurrent euclid

MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture

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Abstract

A new, microcoded, RISC-type system is proposed and presented. The microcode is stored in a 256 x 64 PROM Nanomemory in the CPU. The 8-bit opcode of each instruction is a direct address to the Nanomemory. Each Nanomemory 64-bit word (horizontal microcode) corresponds to a specific machine language instruction. A large 2048 x 32 CPU Register file, using the register window approach, is implemented. A bit-sliced (AMD2900) prototype is currently under construction.