Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
Available instruction-level parallelism for superscalar and superpipelined machines
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
ACM Computing Surveys (CSUR)
Implications of structured programming for machine architecture
Communications of the ACM
The case for the reduced instruction set computer
ACM SIGARCH Computer Architecture News
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
An overview of the MIPS-X-MP project
An overview of the MIPS-X-MP project
Organization and VLSI implementation of MIPS
Organization and VLSI implementation of MIPS
Computer structures: Readings and examples (McGraw-Hill computer science series)
Computer structures: Readings and examples (McGraw-Hill computer science series)
A graphical comparison of RISC processors
ACM SIGARCH Computer Architecture News
Issues in the Design of High Performance SIMD Architectures
IEEE Transactions on Parallel and Distributed Systems
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The initial members of the 88000 family of high-performance 32-bit microprocessor are the 88100 processor and the 88200 cache and memory management unit (CMMU). The processor manipulates integer and floating-point data and initiates instruction and data memory transactions. The CMMU minimizes the latency of main memory requests by maintaining a cache for data transaction and a cache for memory management translations. A typical system consists of one processor and two identical cache chips, one servicing instruction fetch requests, the other servicing data read and write requests. The overall design process for the 88000 family is described, and the integer instructions are discussed. Decisions made with respect to the processor, cache, and software are examined. Some data on the use of the instruction set by the available compilers and the efficiency of the cache and memory systems are presented.