An instruction reoderer for pipelined computers

Authors:
Jong-Jiann Shieh;Christos A. Papachristou
Affiliations:
Department of Information Engineering, Tatung Institute of Technology, Taipei, Taiwan, 10451, R. O. C.;Dept. of Computer Engineering and Science, Case Western Reserve University, Cleveland, Ohio
Venue:
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Year:
1990

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Abstract

In paper [19], we proposed an algorithm to reorder the straight line instruction streams for pipelined computers. In this paper, we extend the algorithm to handle streams with branches and loops as well.The input is the intermediate code of a compiler and is represented by the data control dependence graph(DCG). The DCG is preprocessed to construct a branch nest tree which is related to the structure of the branches and loops within the instruction streams. A priority list is then constructed for scheduling the nodes. The algorithm finds a most suitable slot for each node of the DCG.