Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Advanced compiler optimizations for supercomputers
Communications of the ACM - Special issue on parallelism
Efficient instruction scheduling for a pipelined architecture
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Effectiveness of a machine-level, global optimizer
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Operation scheduling in reconfigurable, multifunction pipelines
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Deterministic Processor Scheduling
ACM Computing Surveys (CSUR)
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Communications of the ACM
Parallel Programming and Compilers
Parallel Programming and Compilers
Dependence graphs and compiler optimizations
POPL '81 Proceedings of the 8th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Coding guidelines for pipelined processors
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
An overview of the PL.8 compiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Dynamic detection of concurrency in DEL instruction streams
Dynamic detection of concurrency in DEL instruction streams
Efficient DAG construction and heuristic calculation for instruction scheduling
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
An instruction reoderer for pipelined computers
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
A brief survey of papers on scheduling for pipelined processors
ACM SIGPLAN Notices
Learning heuristics for basic block instruction scheduling
Journal of Heuristics
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This paper describes a method to reorder the straight line instruction streams for pipelined computers which have one instruction issue unit but may contain multiple function units. The objective is to make the most efficient usage of the pipelines within the computer system. The input to the scheduler is the intermediate code of a compiler, and is represented by a data dependence graph (DDG).The scheduler is a kind of list scheduler. The data dependence and the pipeline effect of the function units within the system have been considered for finding a most suitable time slot for each node during reordering time.The scheduler has been implemented and several scientific application programs have been tested. The results show that in most of the cases the scheduler will achieve the optimal result. The average instruction issue rate is over 96%. As a comparison, the issue rate of an ordinary compiler is only 22%; and the issue rate of a compiler with the effect of pipeline but without reordering the instruction stream is about 45%.