On some variants of the bandwidth minimization problem
SIAM Journal on Computing
Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Efficient instruction scheduling for a pipelined architecture
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Scheduling expressions on a pipelined processor with a maximal delay of one cycle
ACM Transactions on Programming Languages and Systems (TOPLAS)
Scheduling Uet systems on two uniform processors and length two pipelines
SIAM Journal on Computing
Loop quantization of unwinding done right
Proceedings of the 1st International Conference on Supercomputing
Approximation algorithms for scheduling arithmetic expressions on pipelined machines
Journal of Algorithms
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Efficiency of a Good But Not Linear Set Union Algorithm
Journal of the ACM (JACM)
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Code generation and reorganization in the presence of pipeline constraints
POPL '82 Proceedings of the 9th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An overview of the PL.8 compiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Loop Quantization: an Analysis and Algorithm
Loop Quantization: an Analysis and Algorithm
On the Complexity of Precedence Constrained Scheduling
On the Complexity of Precedence Constrained Scheduling
Linear-time, optimal code scheduling for delayed-load architectures
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Low level scheduling using the hierarchical task graph
ICS '92 Proceedings of the 6th international conference on Supercomputing
Foresighted Instruction Scheduling Under Timing Constraints
IEEE Transactions on Computers
Balanced scheduling: instruction scheduling when memory latency is uncertain
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
Efficient instruction scheduling for delayed-load architectures
ACM Transactions on Programming Languages and Systems (TOPLAS)
Balanced scheduling: instruction scheduling when memory latency is uncertain
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Compilers, architectures and synthesis for embedded computing: retrospect and prospect
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Minimizing makespan for a bipartite graph on a single processor with an integer precedence delay
Operations Research Letters
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An instruction or a set of instructions can be considered time critical if their execution is required to free up a resource. Time critical instructions might be used to make shared resources such as registers more quickly available for reuse; or they might be used for real time computations, portions of which are critical for the operation of some piece of equipment. In this paper we present a polynomial time algorithm for optimally scheduling instructions with or without time critical constraints on RISC machines such as the IBM 801, the Berkeley RISC machine, and the HP Precision Architecture. We also show that in the absence of time critical constraints, the greedy algorithm always produces a schedule for a target machine with multiple identical pipelines that has a length less than twice that of an optimal schedule. The behavior of the greedy algorithm is of interest because, as we show, the instruction scheduling problem becomes NP-hard for arbitrary length pipelines, even when the basic block of code being input consists of only several independent streams of straight-line code, and there are no time-critical constraints. Finally, we present the first correct proofs that the problem becomes NP-hard even for small pipelines, no time-critical constraints, and input of several independent streams of straight-line code if there is only a single register or if there is a bus constraint.