Architectural and organizational tradeoffs in the design of the MultiTitan CPU

Authors:
N. P. Jouppi
Affiliations:
Digital Equipment Corporation Western Research Lab, 100 Hamilton Ave., Palo Alto, CA
Venue:
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Year:
1989

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Abstract

This paper describes the architectural and organizational tradeoffs made during the design of the MultiTitan, and provides data supporting the decisions made. These decisions covered the entire space of processor design, from the instruction set and virtual memory architecture through the pipeline and organization of the machine. In particular, some of the tradeoffs involved the use of an on-chip instruction cache with off-chip TLB and floating-point unit, the use of direct-mapped instead of associative caches, the use of 64-bit vs. 32-bit data bus, and the implementation of hardware pipeline interlocks.