Architectural tradeoffs in the design of MIPS-X
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
A DCFL E/D-MESFET GaAs Experimental RISC Machine
IEEE Transactions on Computers
CPC (Cyclic Pipeline Computer)-an Architecture Suited for Josephson and Pipelined-Memory Machines
IEEE Transactions on Computers
Improving single-process performance with multithreaded processors
ICS '96 Proceedings of the 10th international conference on Supercomputing
Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors
Journal of VLSI Signal Processing Systems - Special issue on multimedia signal processing
Practical Delay Enforced Multistream (DEMUS) Control of Deeply Pipelined Processors
IEEE Transactions on Computers
Analytic Performance Modeling for a Spectrum of Multithreaded Processor Architectures
MASCOTS '95 Proceedings of the 3rd International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
The effects of STEF in finely parallel multithreaded processors
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Embedded Systems Design
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The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive ways of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevented by enforcing enough interdispatch delay on each individual stream to prevent successive instructions from interfering with each other's execution. The structure and operation of a small DEMUS processor are presented, and four stream dispatching algorithms are compared by means of a simple simulation. Of the three implementable algorithms, the modified fixed delay (DEMUS/MFD) and encoded delay with fixed minimum (DEMUS/EDF) mechanisms yield the highest performance.