Computer - IEEE Centennial: the state of computing
on Parallel MIMD computation: HEP supercomputer and its applications
on Parallel MIMD computation: HEP supercomputer and its applications
ACM Computing Surveys (CSUR)
A Portable Logic Simulation System for Development of FLATS Machine
Proceedings of the 1983 and 1984 RIMS Symposia on Software Science and Engineering II
Design of a Lisp machine - FLATS
LFP '82 Proceedings of the 1982 ACM symposium on LISP and functional programming
Run-time checking in Lisp by integrating memory addressing and range checking
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Eliminating Interlocks in Deeply Pipelined Processors by Delay Enforced Multistreaming
IEEE Transactions on Computers
Using Horizontal Prefetching to Circumvent the Jump Problem
IEEE Transactions on Computers
Practical Delay Enforced Multistream (DEMUS) Control of Deeply Pipelined Processors
IEEE Transactions on Computers
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Describes a novel computer architecture, called a cyclic pipeline computer (CPC), which is especially suited for Josephson technologies. Since each Josephson logic device acts as a latch, it is possible to use high-pitch and shallow logic pipelining without any increase in delay time and cost. Hence, both the processor and the main memory can be built from the Josephson devices and can be pipelined with the same pipeline pitch time. The CPC supports multiple instruction/multiple data stream (MIMD) by time-sharing the processor and the main memory among multiple instruction streams. In addition, it employs advanced control to speed up the computation for each instruction stream.