The horizon supercomputing system: architecture and software
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
CPC (Cyclic Pipeline Computer)-an Architecture Suited for Josephson and Pipelined-Memory Machines
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Eliminating Interlocks in Deeply Pipelined Processors by Delay Enforced Multistreaming
IEEE Transactions on Computers
Performance Tradeoffs in Multithreaded Processors
IEEE Transactions on Parallel and Distributed Systems
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The simulated performance of a practical multithreaded mechanism for achieving high utilization of deeply pipelined ( 5 stage) processors is presented. Threads are dynamically interleaved in one pipeline. After each instruction is dispatched, enough delay is introduced so that successive instructions cannot interfere. Four scheduling algorithms, three of which are realizable, are tested on a simple simulated processor. Good pipeline utilization can be achieved even when the number of running threads is less than the number of pipeline stages.