A processor architecture for horizon
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Analysis of a 3D toroidal network for a shared memory architecture
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
HORSE: a simulation of the horizon supercomputer
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
A processor architecture for horizon
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Performance prediction for the horizon super computer
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
HORSE: a simulation of the horizon supercomputer
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Efficient Doacross execution on distributed shared-memory multiprocessors
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Fine-grain parallelism in the ALPS programming language
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Characterizing memory hot spots in a shared memory MIMD machine
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Complexity results and algorithms for {
SODA '91 Proceedings of the second annual ACM-SIAM symposium on Discrete algorithms
Processor coupling: integrating compile time and runtime scheduling for parallelism
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Exploiting heterogeneous parallelism on a multithreaded multiprocessor
ICS '92 Proceedings of the 6th international conference on Supercomputing
A Parallel Virtual Machine for Programs Composed of Abstract Data Types
IEEE Transactions on Computers
ICS '90 Proceedings of the 4th international conference on Supercomputing
The impact of synchronization and granularity on parallel systems
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
PiSMA: a parallel VSM architecture
Crossroads
α-coral: a multigrain, multithreaded processor architecture
ICS '01 Proceedings of the 15th international conference on Supercomputing
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Practical Delay Enforced Multistream (DEMUS) Control of Deeply Pipelined Processors
IEEE Transactions on Computers
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
Multithreaded Parallel Computer Model with Performance Evaluation
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
MemTracker: An accelerator for memory debugging and monitoring
ACM Transactions on Architecture and Code Optimization (TACO)
Exploring irregular memory accesses on FPGAs
Proceedings of the first workshop on Irregular applications: architectures and algorithm
Compiled multithreaded data paths on FPGAs for dynamic workloads
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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Horizon is the name currently being used to refer to a shared-memory Multiple Instruction stream - Multiple Data stream (MIMD) computer architecture under study by independent groups at the Supercomputing Research Center and at Tera Computer Company. Its performance target is a sustained rate of 100 giga (1011) Floating Point Operations Per Second (FLOPS). Horizon achieves this speed with a few hundred identical scalar processors. Each processor has a horizontal instruction set that allows the production of one or more floating point results per cycle without resorting to vector operations. Memory latency is hidden, assuming enough parallelism is available, by allowing processors to switch context on each machine cycle.In this overview, the Horizon architecture is introduced and its performance is estimated. The processor instruction set and a simple programming example are given. Additional details on the processor architecture, interconnection network design, performance analyses, machine simulator, compiler development, and application studies can be found in companion papers.