on Parallel MIMD computation: HEP supercomputer and its applications
Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
The horizon supercomputing system: architecture and software
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
The horizon supercomputing system: architecture and software
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
A processor architecture for horizon
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Complexity results and algorithms for {
SODA '91 Proceedings of the second annual ACM-SIAM symposium on Discrete algorithms
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Compiler research to test several hardware features of the Horizon supercomputer design has yielded some preliminary results based solely on code generation and local optimization. Correctly packing operations into the moderately wide instruction word seems relatively straightforward, and there is nothing to suggest that it will be impossible to discover a good heuristic for instruction scheduling. Lookahead values are easy to compute within basic blocks, but they have not yet been tested across block boundaries, and the overall efficacy of this hardware feature has not been proved. Static analysis shows that the arithmetic unit is noticeably busier than the control unit, but this apparent imbalance may disappear once global optimization permits reasonable dynamic analysis of compiler output. Similarly, it is too early to determine either the adequacy of 32 registers or the usefulness of multiple target registers and condition codes.