Multithreaded Parallel Computer Model with Performance Evaluation

Authors:
JiangTao Cui;Jacir L. Bordim;Koji Nakano;Tatsuya Hayashi;Naohiro Ishii
Affiliations:
-;-;-;-;-
Venue:
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Year:
2000

Citing 10
Cited 1

MASA: a multithreaded processor architecture for parallel symbolic computing

ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The horizon supercomputing system: architecture and software

Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Computer architecture: a quantitative approach

Computer architecture: a quantitative approach
Multithreading: a revisionist view of dataflow architectures

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
An introduction to parallel algorithms

An introduction to parallel algorithms
Monsoon: an explicit token-store architecture

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Efficient Parallel Algorithms

Efficient Parallel Algorithms
Datarol: A Parallel Machine Architecture for Fine-Grain Multithreading

MPPM '97 Proceedings of the Conference on Massively Parallel Programming Models
A Fine-Grain Multithreading Superscalar Architecture

PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation

PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques

Performance modeling and analysis of correlated parallel computations

Parallel Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

The main contribution of this work is to in troducea multithreaded parallel computer model (MPCM), whic hhas a number of multithreaded processors connected with an interconnection network. We have implemented some fundamental PRAM algorithms, such as prefix sums and list ranking algorithms, and evaluated their performance. These algorithms achiev ed optimal speedup up to at least 16 processors.