A Fine-Grain Multithreading Superscalar Architecture

  • Authors:
  • Mat Loikkanen;Nader Bagherzadeh

  • Affiliations:
  • -;-

  • Venue:
  • PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
  • Year:
  • 1996

Quantified Score

Hi-index 0.00

Visualization

Abstract

In this study we show that fine-grain multithreading is an effective way to increase instruction-level parallelism and hide the latencies of long-latency operations in a superscalar processor. The effects of long-latency operations, such as remote memory references, cache-misses, and multi-cycle floating-point calculations, are detrimental to performance since such operations typically cause a stall. Even superscalar processors, that are capable of performing various operations in parallel, are vulnerable. A fine-grain multithreading paradigm and unique multithreaded superscalar architecture is presented. Simulation results show significant speedup over single-threaded superscalar execution.