DISC: dynamic instruction stream computer
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
An elementary processor architecture with simultaneous instruction issuing from multiple threads
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Interleaving: a multithreading technique targeting multiprocessors and workstations
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
The effectiveness of multiple hardware contexts
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Practical UNIX programming: a guide to concurrency, communication, and multithreading
Practical UNIX programming: a guide to concurrency, communication, and multithreading
Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
ICS '90 Proceedings of the 4th international conference on Supercomputing
An analysis of database workload performance on simultaneous multithreaded processors
Proceedings of the 25th annual international symposium on Computer architecture
A simultaneous multithreading simulator
ACM SIGARCH Computer Architecture News
Multi-processor performance on the Tera MTA
SC '98 Proceedings of the 1998 ACM/IEEE conference on Supercomputing
A Study of a Simultaneous Multithreaded Processor Implementation
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Identifying Bottlenecks in a Multithreaded Superscalar Microprocessor
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
Performance Study of a Multithreaded Superscalar Microprocessor
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
A Fine-Grain Multithreading Superscalar Architecture
PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
Classification and Performance Evaluation of Simultaneous Multithreaded Architectures
HIPC '97 Proceedings of the Fourth International Conference on High-Performance Computing
Simultaneous Multithreaded Vector Architecture: Merging ILP and DLP for High Performance
HIPC '97 Proceedings of the Fourth International Conference on High-Performance Computing
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Nowadays, SMT (Simultaneous Multithreaded) architectures use aggressive techniques to execute instructions from different threads on shared resources simultaneously. SEMPRE is a type of SMT architecture, which was proposed to schedule and execute processes simultaneously. The waste of time on both process scheduling and context switching is minimal, providing high performance during the execution of applications. SEMPRE architecture was analyzed and evaluated using execution driven simulation of SPEC benchmark suit. The simulations showed that process scheduling by hardware can provide reasonable performance over process scheduling by operating system on equivalent simultaneous multithreaded architectures, with little extra hardware. This higher performance is achieved because the hardware makes better use of process time-slice. The performance of SEMPRE is always higher than performance of traditional SMT, overcoming 21% in some cases.