Improving SMT performance scheduling processes
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
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The simultaneous multithreaded [1] architecture is an extension of the single-threaded architecture that helps hide the performance penalty created by long-latency instructions, branch mispredictions, and memory accesses. Simultaneous multithreaded architectures use a more flexible parallelism, which takes advantage of both instruction-level, and thread-level parallelism. Additionally, it tends to promote better utilization of available functional units. A model of a simultaneous multithreaded architecture was designed, simulated, and analyzed in order to evaluate design alternatives. The simulator was created by modifying a version of the Simple Scalar tool set, developed at the University of Wisconsin. The simulations provide documentation for an overall system performance improvement of a simultaneous multithreaded architecture. In early simulation results, performed with the same number of functional units, an improvement in the number of instructions per cycle (IPC) of between 43% and 58% was found using four threads versus a single thread.