Fundamentals of queueing theory (2nd ed.).
Fundamentals of queueing theory (2nd ed.).
A processor architecture for horizon
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Analysis of multithreaded architectures for parallel computing
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Eliminating Interlocks in Deeply Pipelined Processors by Delay Enforced Multistreaming
IEEE Transactions on Computers
An elementary processor architecture with simultaneous instruction issuing from multiple threads
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
APRIL: a processor architecture for multiprocessing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Computer Performance Modeling Handbook
Computer Performance Modeling Handbook
Performance Tradeoffs in Multithreaded Processors
IEEE Transactions on Parallel and Distributed Systems
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
Shared Resource Multiprocessing
Computer
| Hi-index | 0.00 |
The throughput of pipelined processors suffers from delays associated with instruction dependencies and memory latencies. Multithreaded architectures attempt to hide such delays by sharing the processor with multiple instruction streams. In this paper we develop a comprehensive analytic framework to quantitatively evaluate the performance of a wide spectrum of mulithreaded machines, ranging from those that are capable of switching threads every cycle to those that switch threads only on long delays. The models are validated against previously published simulation and modeling results, and then used to assess the performance potential of multithreading given current processor technology.