Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
Architectural tradeoffs in the design of MIPS-X
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Programming parallel processors
Programming parallel processors
ACM Computing Surveys (CSUR)
Architecture of high performance computers: vol. 1
Architecture of high performance computers: vol. 1
A microcoded real-time executive for numeric support nodes distributed within embedded networks
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
An architecture of a dataflow single chip processor
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Optimal Robust Compression of Test Responses
IEEE Transactions on Computers
Graph coloring register allocation for processors with multi-register operands
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
Monsoon: an explicit token-store architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Communications of the ACM
Communicating sequential processes
Communications of the ACM
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A data flow processor array system: Design and analysis
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
General microprogram width reduction using generator sets
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
Organization and VLSI implementation of MIPS
Organization and VLSI implementation of MIPS
Simultaneous signature and syndrome compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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