Communications of the ACM - Special issue on computer architecture
List Processing with a Data Flow Machine
Proceedings of RIMS Symposium on Software Science and Engineering
A multiple processor data flow machine that supports generalized procedures
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Implementation and evaluation of a list-processing-oriented data flow machine
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Evaluation of a prototype data flow processor of the SIGMA-1 for scientific computations
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Dataflow Computing Models, Languages, and Machines for Intelligence Computations
IEEE Transactions on Software Engineering - Special Issue on Artificial Intelligence in Software Applications
Executing a Program on the MIT Tagged-Token Dataflow Architecture
IEEE Transactions on Computers
Efficient routing techniques for cooperating processors in dataflow computers
CSC '90 Proceedings of the 1990 ACM annual conference on Cooperation
GT-EP: a novel high-performance real-time architecture
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Dataflow computer development in Japan
ICS '90 Proceedings of the 4th international conference on Supercomputing
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
A History of Data-Flow Languages
IEEE Annals of the History of Computing
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This paper presents the architecture of a highly parallel processor array system which executes programs by means of a data driven control mechanism. The data driven control mechanism makes it easy to construct an MIMD (multiple instruction stream and multiple data stream) system, since it unifies inter-processor data transfer and intra-processor execution control. The design philosophy of the data flow processor array system presented in this paper is to achieve high performance by adapting a system structure to operational characteristics of application programs, and also to attain flexibility through executing instructions based on a data driven mechanism. The operational characteristics of the proposed system are analyzed using a probability model of the system behavior. Comparing the analytical results with the simulation results through an experimental hardware system, the results of the analysis clarify the principal effectiveness of the proposed system. This system can achieve high operation rates and is neither sensitive to inter-processor communication delay nor sensitive to system load imbalance.