Building blocks for data flow prototypes
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
The architecture and system method of DDM1: A recursively structured Data Driven Machine
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
VAL- ORIENTED ALGORITHMIC LANGUAGE, PRELIMINARY REFERENCE MANUAL
VAL- ORIENTED ALGORITHMIC LANGUAGE, PRELIMINARY REFERENCE MANUAL
ACM Computing Surveys (CSUR)
Analytical modeling and architectural modifications of a dataflow computer
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Architectural issues in designing symbolic processors in optics
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
VLSI design of a one-chip data-driven processor: Q-v1
ACM '87 Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow
Conception, evolution, and application of functional programming languages
ACM Computing Surveys (CSUR)
Analysis of computation-communication issues in dynamic dataflow architectures
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Performance Evaluation of a Dataflow Architecture
IEEE Transactions on Computers
A basic architecture supporting LGDG computation
ICS '90 Proceedings of the 4th international conference on Supercomputing
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Fine-Grained Multithreading with Process Calculi
IEEE Transactions on Computers - Special issue on the parallel architecture and compilation techniques conference
Para-functional programming: a paradigm for programming multiprocessor systems
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Run-Time Disambiguation: Coping with Statically Unpredictable Dependencies
IEEE Transactions on Computers
A Foreword to Knowledge and Data Engineering
IEEE Transactions on Knowledge and Data Engineering
A Hybrid Scheme for Processing Data Structures in a Dataflow Environment
IEEE Transactions on Parallel and Distributed Systems
DDDP-a Distributed Data Driven Processor
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A data flow processor array system: Design and analysis
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A data flow architecture with a paged memory system
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A critique of multiprocessing von Neumann style
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A multi-microprocessor architecture with hardware support for communication and scheduling
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Design and Performance Evaluation of EXMAN: An EXtended MANchester Data Flow Computer
IEEE Transactions on Computers
Measuring the Parallelism Available for Very Long Instruction Word Architectures
IEEE Transactions on Computers
Hardware budget and runtime system for data-driven multithreaded chip multiprocessor
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
A new programming paradigm inspired by artificial chemistries
UPP'04 Proceedings of the 2004 international conference on Unconventional Programming Paradigms
Patchwork: A fast interpreter for a restricted dataflow language
Journal of Systems and Software
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Programs for data flow machines are written in functional languages, some of which require efficient support for dynamic procedure invocation to achieve high performance and programming flexibility. Among the proposed data flow machines, few support procedures in any generality. Our machine, which is a hardware realization of the U-interpreter for data flow languages, provides support for a variety of procedure calling conventions. Because the U-interpreter assigns a unique activity name to each instance of a computation (activity), an activity name may become arbitrarily large in the case of nested or recursive procedure calls. Hardware considerations, however, require that an activity name be represented by a fixed-size tag. We describe a mechanism that uses fixed-size, reusable tags in hardware. Like processor and memory resources, a group of tags is allocated and deallocated for each procedure activation. The proposed mechanism passes procedure arguments and results efficiently, given the distributed environment of our machine.