First version of a data flow procedure language
Programming Symposium, Proceedings Colloque sur la Programmation
A multiple processor data flow machine that supports generalized procedures
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
A multi-user data flow architecture
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Building blocks for data flow prototypes
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
The architecture and system method of DDM1: A recursively structured Data Driven Machine
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
VAL- ORIENTED ALGORITHMIC LANGUAGE, PRELIMINARY REFERENCE MANUAL
VAL- ORIENTED ALGORITHMIC LANGUAGE, PRELIMINARY REFERENCE MANUAL
Processor Scheduling for Linearly Connected Parallel Processors
IEEE Transactions on Computers
Evaluation of a prototype data flow processor of the SIGMA-1 for scientific computations
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Dataflow Computing Models, Languages, and Machines for Intelligence Computations
IEEE Transactions on Software Engineering - Special Issue on Artificial Intelligence in Software Applications
Dataflow computer development in Japan
ICS '90 Proceedings of the 4th international conference on Supercomputing
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Area-Performance Trade-offs in Tiled Dataflow Architectures
Proceedings of the 33rd annual international symposium on Computer Architecture
Modeling instruction placement on a spatial architecture
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Instruction scheduling for a tiled dataflow architecture
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
ACM Transactions on Computer Systems (TOCS)
| Hi-index | 0.00 |
This paper describes an architecture of a data flow computer named the Distributed Data Driven Processor (DDDP), and presents an experimental system and the results of experiments using several benchmarks. The experimental system has four processing elements connected by a ring bus, and a structured data memory. The main features of our system are that each processing element is provided with a hardware hashing mechanism to implement token coloring, and a ring bus is used to pass tokens concurrently among processing elements. A hardware monitor was used to measure the performance of the experimental system. The experimental system adopts a low key technology and yet is capable of executing about 0.7 million instructions per second through the benchmarks. This implies that data flow computers can be alternative to the conventional von-Neumann computers if state-of-the-art technologies are adequately introduced.