The Organization of Microprogram Stores
ACM Computing Surveys (CSUR)
Principles Firmware Engineering
Principles Firmware Engineering
Compressing control ROM for VLSI microprogrammed microprocessors
MICRO 13 Proceedings of the 13th annual workshop on Microprogramming
Microprogrammed implementation of a single chip microprocessor
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
A customized control store design in microprogrammed control units
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
A case study in using two-level control stores
ACM SIGMICRO Newsletter
GT-EP: a novel high-performance real-time architecture
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
A case study in using two-level control stores
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
PRONTO: Quick PLA product reduction
DAC '83 Proceedings of the 20th Design Automation Conference
Toward type-oriented dynamic vertical migration
ACM SIGMICRO Newsletter
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The problem of reducing the microinstruction length for a parallel microprogram, by trading off microprogram width (bits) for subsequent logic, is considered. In a generalization of previous methods, it is shown that a considerable reduction of microprogram storage size can be achieved by selecting a subset of the original microorders to serve as inputs to some generating logic in order to provide all the microorders in the original microprogram. Heuristic solution methods are shown, along with ways to control the bounds of the solutions, allowing the designer the choice between a fast solution and an optimal solution. Examples show the effects of using these methods, alone and in conjunction with previously published methods for width reduction. Applications of the width reduction technique to reasonable modern design situations are discussed.