An architecture framework for application-specific and scalable architectures

Authors:
J. M. Mulder;R. J. Portier;A. Srivastava;R. in't Velt
Affiliations:
Section Digital Systelns and Computer Architecture, Department of Electrical Engineering, Delft University of Technology, POBox 5031,260O AG Delft, The Netherlands;Section Digital Systelns and Computer Architecture, Department of Electrical Engineering, Delft University of Technology, POBox 5031,260O AG Delft, The Netherlands;Section Digital Systelns and Computer Architecture, Department of Electrical Engineering, Delft University of Technology, POBox 5031,260O AG Delft, The Netherlands;Section Digital Systelns and Computer Architecture, Department of Electrical Engineering, Delft University of Technology, POBox 5031,260O AG Delft, The Netherlands
Venue:
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Year:
1989

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Abstract

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture.The SCalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the application-specific architecture;This paper concentrates primarily on the architecture framework of SCARCE, but also presents briefly some software issues and outlines the process of generating VLSI processors.