Cost-effective design of application specific VLIW processors using the SCARCE framework

  • Authors:

  • H. Mulder;R. J. Portier

  • Affiliations:

  • Section Digital Systems and Computer Architecture, Department of Electrical Engineering, Delft University of Technology, P.O. Box 5031, 2600 GA Delft, The Netherlands;Section Digital Systems and Computer Architecture, Department of Electrical Engineering, Delft University of Technology, P.O. Box 5031, 2600 GA Delft, The Netherlands

  • Venue:
  • MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
  • Year:
  • 1989

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Abstract

Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs; especially in the case of low-volume productions. The flexibility of horizontal-microcoded machines allows these costs to be reduced, but the flexibility often reduces efficiency. VLIW is a new and promising concept for the design of low-cost, high-performance parallel computer systems. We suggest that the VLIW concept can also be used as a basis for cost-effective design of application-specific processors which must exploit application-resident parallelism.The SCARCE (SCalable ARChitecture Experiment) framework, an approach for cost-effective design of application-specific processors, provides features which allow the design of retargetable VLIW architectures. However, a retargetable VLIW architecture is only effective if there is a retargetable VLIW compiler. Since a VLIW compiler is an essential part of the VLIW architecture, tradeoffs must be made between the variety of VLIW architectures and the compiler complexity. We suggest that limiting the flexibility of the retargetable VLIW architecture does not necessary reduce the application space.This paper discusses the issues related to the design of a retargetable VLIW processor architecture and compiler within the SCARCE framework.