DAC '83 Proceedings of the 20th Design Automation Conference
Exploiting parallel microprocessor microarchitectures with a compiler code generator
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Achieving high instruction cache performance with an optimizing compiler
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The effects of processor architecture on instruction memory traffic
ACM Transactions on Computer Systems (TOCS)
Computer - Special issue on experimental research in computer architecture
Fast instruction cache performance evaluation using compile-time analysis
SIGMETRICS '92/PERFORMANCE '92 Proceedings of the 1992 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Processor Architecture and Data Buffering
IEEE Transactions on Computers
Execution-driven simulation of multiprocessors: address and timing analysis
ACM Transactions on Modeling and Computer Simulation (TOMACS)
EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Implementation-Independent Model of an Instruction Set Architecture in VHDL
IEEE Design & Test
Bridge: a retargetable extensive profiling tool
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
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The authors present a high-level simulator that supports a top-down architectural analysis of embedded, custom applications. This tool characterizes more than 50 instruction-set variants and allows data such as instruction cached performance, data cache performance, register set size, and register allocation policy to be evaluated for all the architectures simultaneously. Designers also have more flexibility because they can trade off among high-level design constructs. Thus, they can evaluate relative performance before having to complete the machine specification at a lower level.