Processor architecture and cache performance
Processor architecture and cache performance
Cache memory optimization to reduce processor/memory traffic
Advances in VLSI and Computer Systems
The effect of instruction set complexity on program size and memory performance
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Analysis of cache performance for operating systems and multiprogramming
Analysis of cache performance for operating systems and multiprogramming
Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
ACM Computing Surveys (CSUR)
A Workbench for Computer Architects
IEEE Design & Test
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Experimental evaluation of on-chip microprocessor cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An evaluation of code space requirements and performance of various architectures
ACM SIGARCH Computer Architecture News
Processor Architecture and Data Buffering
IEEE Transactions on Computers
Optimization of instruction fetch mechanisms for high issue rates
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The Effect of Code Expanding Optimizations on Instruction Cache Design
IEEE Transactions on Computers
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The relative amount of instruction traffic for two architectures is about the same in the presence of a large cache as with no cache. Furthermore, the presence of an intermediate-sized cache probably substantially favors the denser architecture. Encoding techniques have a much greater impact on instruction traffic than do the differences between instruction set families such as stack and register set. However, register set architectures have somewhat lower instruction traffic than directly comparable stack architectures of some local variables are allocated in registers. This study has clearly indicated that cache factors should be taken into consideration when making architectural tradeoffs. The differences in memory traffic between two architectures may be greatly amplified in the presence of a cache.