Code selection through object code optimization
ACM Transactions on Programming Languages and Systems (TOPLAS) - Lecture notes in computer science Vol. 174
A retargetable instruction reorganizer
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
The Generation of Optimal Code for Arithmetic Expressions
Journal of the ACM (JACM)
ACM Computing Surveys (CSUR)
Implications of structured programming for machine architecture
Communications of the ACM
Software Tools
The case for the reduced instruction set computer
ACM SIGARCH Computer Architecture News
Coding guidelines for pipelined processors
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
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ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
An overview of the PL.8 compiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
A Characterization of Processor Performance in the vax-11/780
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
ACM SIGPLAN Notices
Instruction-path coprocessing to solve some RISC problems
ACM SIGARCH Computer Architecture News
The impact of code density on instruction cache performance
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Profile guided code positioning
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
The effects of processor architecture on instruction memory traffic
ACM Transactions on Computer Systems (TOCS)
Performance issues in correlated branch prediction schemes
Proceedings of the 28th annual international symposium on Microarchitecture
The Effect of Code Expanding Optimizations on Instruction Cache Design
IEEE Transactions on Computers
Code Positioning for VLIW Architectures
HPCN Europe 2001 Proceedings of the 9th International Conference on High-Performance Computing and Networking
An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Profile guided code positioning
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Reducing code size through address register assignment
ACM Transactions on Embedded Computing Systems (TECS)
Address register assignment for reducing code size
CC'03 Proceedings of the 12th international conference on Compiler construction
Code density concerns for new architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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One potential disadvantage of a machine with a reduced instruction set is that object programs may be substantially larger than those for a machine with a richer, more complex instruction set. The main reason is that a small instruction set will require more instructions to implement the same function. In addition, the tendency of RISC machines to use fixed length instructions with a few instruction formats also increases object program size. It has been conjectured that the resulting larger programs could adversely affect memory performance and bus traffic. In this paper we report the results of a set of experiments to isolate and determine the effect of instruction set complexity on cache memory performance and bus traffic. Three high-level language compilers were constructed for machines with instruction sets of varying degrees of complexity. Using a set of benchmark programs, we evaluated the effect of instruction set complexity had on program size. Five of the programs were used to perform a set of trace-driven simulations to study each machine's cache and bus performance. While we found that the miss ratio is affected by object program size, it appears that this can be corrected by simplying increasing the size of the cache. Our measurements of bus traffic, however, show that even with large caches, machines with simple instruction sets can expect substantially more main memory reads than machines with dense object programs.