Microprocessor architectures: a comparison based on code generation by compiler
Communications of the ACM
Language coprocessor to support the interpretation of Modula-2 programs
Microprocessors & Microsystems
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
The effect of instruction set complexity on program size and memory performance
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
BYTE
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
The case for the reduced instruction set computer
ACM SIGARCH Computer Architecture News
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Recent research in computer architecture has led to the development of Reduced Instruction Set Computers (RISCs). Such computers exploit the fast execution of a low number of low-level instructions. However, two problems arise: (i) as the RISC instruction set architectures are completely new and use specific look-ahead techniques, optimizing code generators of compilers must be developed from scratch to allow high level language programming; (ii) the high execution rate and low semantic instruction content inherent to RISCs requires extremely high instruction bandwidth in order to achieve maximal throughput. In this paper we propose to apply the concept of coprocessing in the instruction path and show how this technique, in particular in the RISC-case, greatly contributes to the solution of the two above problems.