Address register assignment for reducing code size

  • Authors:

  • M. Kandemir;M. J. Irwin;G. Chen;J. Ramanujam

  • Affiliations:

  • CSE Department, Pennsylvania State University, University Park, PA;CSE Department, Pennsylvania State University, University Park, PA;CSE Department, Pennsylvania State University, University Park, PA;ECE Department, Louisiana State University, Baton Rouge, LA

  • Venue:
  • CC'03 Proceedings of the 12th international conference on Compiler construction
  • Year:
  • 2003

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Abstract

In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55&percnt). This work presents a compiler-based optimization strategy to reduce the code size in embedded systems. Our strategy maximizes the use of indirect addressing modes with post-increment and post-decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring).