Program optimization for instruction caches
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Achieving high instruction cache performance with an optimizing compiler
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The case for the sustained performance computer architecture
ACM SIGARCH Computer Architecture News
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Cache and memory hierarchy design: a performance-directed approach
Cache and memory hierarchy design: a performance-directed approach
High-performance computer architecture (2nd ed.)
High-performance computer architecture (2nd ed.)
The Evolution of Instruction Sequencing
Computer - Special issue on instruction sequencing
An instruction memory organization for high-performance instruction sequencing
An instruction memory organization for high-performance instruction sequencing
IEEE Spectrum - Supercomputing
An evaluation of the uses of program control flow information in instruction memory hierarchies: prefetching and predictability
ACM Computing Surveys (CSUR)
Aspects of Cache Memory and Instruction
Aspects of Cache Memory and Instruction
ACM SIGARCH Computer Architecture News
SPAID: software prefetching in pointer- and call-intensive environments
Proceedings of the 28th annual international symposium on Microarchitecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Evaluation of multithreaded uniprocessors for commercial application environments
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
ACM SIGARCH Computer Architecture News
Run-time adaptive cache hierarchy management via reference analysis
Proceedings of the 24th annual international symposium on Computer architecture
Run-time spatial locality detection and optimization
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Characterization and improvement of load/store cache-based prefetching
ICS '98 Proceedings of the 12th international conference on Supercomputing
Exploiting spatial locality in data caches using spatial footprints
Proceedings of the 25th annual international symposium on Computer architecture
Hardware-software trade-offs in a direct Rambus implementation of the RAMpage memory hierarchy
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
IEEE Transactions on Computers
Profile-directed restructuring of operating system code
IBM Systems Journal
Proceedings of the 4th ACM international conference on Embedded software
Compiler optimization to improve data locality for processor multithreading
Scientific Programming
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By examining the rate at which successive generations of processor and DRAM cycle times have been diverging over time, we can track the latency problem of computer memory systems. Our research survey starts with the fundamentals of single-level caches and moves to the need for multilevel cache hierarchies. We look at some of the current techniques for boosting cache performance, especially compiler-based methods for code restructuring and instruction and data prefetching. These two areas will likely yield improvements for a much larger domain of applications in the future.