A variable instruction stream extension to the VLIW architecture
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Alternative implementations of two-level adaptive branch prediction
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Improving the accuracy of dynamic branch prediction using branch correlation
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
The multiscalar architecture
Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Dynamic path-based branch correlation
Proceedings of the 28th annual international symposium on Microarchitecture
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Speculative execution via address prediction and data prefetching
ICS '97 Proceedings of the 11th international conference on Supercomputing
Dynamic speculation and synchronization of data dependences
Proceedings of the 24th annual international symposium on Computer architecture
Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
Path-based next trace prediction
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The predictability of data values
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Value speculation scheduling for high performance processors
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Partitioning parallel programs for macro-dataflow
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
Effective Hardware-Based Data Prefetching for High-Performance Processors
IEEE Transactions on Computers
Exploring Microprocessor Architectures for Gigascale Integration
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Profiling for Input Predictable Threads
ICCD '98 Proceedings of the International Conference on Computer Design
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor
Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor
Compiling for the multiscalar architecture
Compiling for the multiscalar architecture
A dynamic multithreading processor
A dynamic multithreading processor
Design of a Computer—The Control Data 6600
Design of a Computer—The Control Data 6600
Enhancing software reliability with speculative threads
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Parallel simulation of chip-multiprocessor architectures
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Multiple-path execution for chip multiprocessors
Journal of Systems Architecture: the EUROMICRO Journal
Scaling Up the Atlas Chip-Multiprocessor
IEEE Transactions on Computers
Executing irregular scientific applications on stream architectures
Proceedings of the 21st annual international conference on Supercomputing
On the potential of latency tolerant execution in speculative multithreading
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
A pattern language for parallelizing irregular algorithms
Proceedings of the 2010 Workshop on Parallel Programming Patterns
Disjoint out-of-order execution processor
ACM Transactions on Architecture and Code Optimization (TACO)
| Hi-index | 14.98 |
Single-chip multiprocessors are an important research direction for future microprocessors. The stigma of this approach is that many important applications cannot be automatically parallelized. This paper presents a single-chip multiprocessor that engages aggressive speculation techniques to enable dynamic parallelization of irregular, sequential binaries. Thread speculation and data value prediction are combined to enable the processor to execute dependent threads in parallel. The architecture performs a novel form of dynamic thread partitioning and includes an aggressive correlated value predictor. Microarchitectural structures manage interthread data and control dependencies. On an eight processor system, simulated execution of SPECint95 binaries delivers a speedup of 3.4 over a scalar in-order uniprocessor. This improvement is due entirely to the exploitation of dynamically extracted thread level parallelism.