Multiple-path execution for chip multiprocessors

Authors:
Matthew C. Chidester;Alan D. George;Matthew A. Radlinski
Affiliations:
High-Performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL;High-Performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL;High-Performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2003

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Abstract

The increased dependence of clock cycle time on interconnect delay favors chip multiprocessors (CMP) for future microprocessor designs. This paper studies multiple-path execution (MPE) on a CMP to provide speedup on unmodified sequential code by exploring different paths of a conditional branch on separate processors. MPE performance due to processor complexity and count, cache and branch prediction architecture, processor-to-path allocation strategies, and limited interprocessor communication capabilities is explored. Simulation shows 12.7% speedup of SPECint95 with up to 33.5% on components with poor branch prediction accuracy using an 8-processor, 8-issue CMP with a simple mesh interconnect, realistic latencies, and limited bandwidth.