Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
Modern mathematical statistics
Modern mathematical statistics
The Stack Growth Function: Cache Line Reference Models
IEEE Transactions on Computers
IEEE Transactions on Computers
Alternative implementations of two-level adaptive branch prediction
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Optimization of instruction fetch mechanisms for high issue rates
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Multiple-block ahead branch predictors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Superblock formation using static program analysis
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Path-based next trace prediction
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors
IEEE Transactions on Parallel and Distributed Systems
Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes
IEEE Transactions on Computers
A Trace Cache Microarchitecture and Evaluation
IEEE Transactions on Computers - Special issue on cache memory and related problems
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Analytical Modeling of Set-Associative Cache Behavior
IEEE Transactions on Computers
Dynamic space-sharing in computer systems
Communications of the ACM
The working set model for program behavior
Communications of the ACM
Performance Tradeoffs in Multithreaded Processors
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the conference on Design, automation and test in Europe
Trace cache design for wide-issue superscalar processors
Trace cache design for wide-issue superscalar processors
Trace cache in simultaneous multithreading
Trace cache in simultaneous multithreading
Architectural extensions for executing coherence protocols on multi-threaded processors with integrated memory controllers
Microarchitecture modeling for design-space exploration
Microarchitecture modeling for design-space exploration
Data prefetching via speculative precomputation on a simultaneous multithreaded processor
Data prefetching via speculative precomputation on a simultaneous multithreaded processor
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Trace Scheduling: A Technique for Global Microcode Compaction
IEEE Transactions on Computers
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Instruction fetch mechanism is a performance bottleneck of Superscalar and Simultaneous Multithreading Processors. A hardware mechanism, known as Trace Cache, is used in several processor architectures to improve instruction fetch performance. Most studies on Trace Cache architectures are based on simulation of benchmark programs. Analytical studies on Trace Cache and Trace Cache Miss Rates are rare. This paper presents a new analytical model of Trace Cache Miss Rate. The presented model can be used to understand performance and tradeoffs in Trace Cache design. The presented study is the first of its kind, which provides clearer understanding of Trace Cache performance for designers, students, and researchers.