Hardware support for large atomic units in dynamically scheduled machines

  • Authors:

  • S. W. Melvin;M. C. Shebanow;Y. N. Patt

  • Affiliations:

  • Computer Science Division, University of California, Berkeley, Berkeley, CA;Computer Science Division, University of California, Berkeley, Berkeley, CA;Computer Science Division, University of California, Berkeley, Berkeley, CA

  • Venue:
  • MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
  • Year:
  • 1988

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Abstract

Microarchitectures that implement conventional instruction set architectures are usually limited in that they are only able to execute a small number of microoperations concurrently. This limitation is due in part to the fact that the units of work that the hardware treats as indivisible are small. While this limitation is not important for microarchitectures with a low level of functionality, it can be significant if the goal is to build hardware that can support a large number of microoperations executing concurrently. In this paper we address the tradeoffs associated with the sizes of the various units of work that a processor considers indivisible, or atomic. We argue that by allowing larger units of work to be atomic, restrictions on concurrent operation are reduced and performance is increased. We outline the implementation of a front end for a dynamically scheduled processor with hardware support for large atomic units. We discuss tradeoffs in the design and show that with a modest investment in hardware, the run-time advantages of large atomic units can be realized without the need to alter the instruction set architecture.