The STAMPede approach to thread-level speculation

  • Authors:

  • J. Gregory Steffan;Christopher Colohan;Antonia Zhai;Todd C. Mowry

  • Affiliations:

  • University of Toronto, Ontario, Canada;Carnegie Mellon University, Pittsburgh, PA;University of Minnesota, Minneapolis, MN;Carnegie Mellon University, Pittsburgh, PA

  • Venue:
  • ACM Transactions on Computer Systems (TOCS)
  • Year:
  • 2005

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Abstract

Multithreaded processor architectures are becoming increasingly commonplace: many current and upcoming designs support chip multiprocessing, simultaneous multithreading, or both. While it is relatively straightforward to use these architectures to improve the throughput of a multithreaded or multiprogrammed workload, the real challenge is how to easily create parallel software to allow single programs to effectively exploit all of this raw performance potential. One promising technique for overcoming this problem is Thread-Level Speculation (TLS), which enables the compiler to optimistically create parallel threads despite uncertainty as to whether those threads are actually independent. In this article, we propose and evaluate a design for supporting TLS that seamlessly scales both within a chip and beyond because it is a straightforward extension of write-back invalidation-based cache coherence (which itself scales both up and down). Our experimental results demonstrate that our scheme performs well on single-chip multiprocessors where the first level caches are either private or shared. For our private-cache design, the program performance of two of 13 general purpose applications studied improves by 86% and 56%, four others by more than 8%, and an average across all applications of 16%---confirming that TLS is a promising way to exploit the naturally-multithreaded processing resources of future computer systems.