MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

  • Authors:
  • Khubaib;M. Aater Suleman;Milad Hashemi;Chris Wilkerson;Yale N. Patt

  • Affiliations:
  • -;-;-;-;-

  • Venue:
  • MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2012

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Abstract

Several researchers have recognized in recent years that today's workloads require a micro architecture that can handle single-threaded code at high performance, and multi-threaded code at high throughput, while consuming no more energy than is necessary. This paper proposes Morph Core, a unique approach to satisfying these competing requirements, by starting with a traditional high performance out-of-order core and making minimal changes that can transform it into a highly-threaded in-order SMT core when necessary. The result is a micro architecture that outperforms an aggressive 4-way SMT out-of-order core, "medium" out-of-order cores, small in-order cores, and Core Fusion. Compared to a 2-way SMT out-of-order core, Morph Core increases performance by 10% and reduces energy-delay-squared product by 22%.