Increasing the instruction fetch rate via multiple branch prediction and a branch address cache
ICS '93 Proceedings of the 7th international conference on Supercomputing
Optimization of instruction fetch mechanisms for high issue rates
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Trace cache: a low latency approach to high bandwidth instruction fetching
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
Alternative implementations of two-level adaptive branch prediction
25 years of the international symposia on Computer architecture (selected papers)
Way-predicting set-associative cache for high performance and low energy consumption
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Reducing set-associative cache energy via way-prediction and selective direct-mapping
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Energy-aware fetch mechanism: trace cache and BTB customization
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
IEEE Computer Architecture Letters
Evaluating trace cache energy efficiency
ACM Transactions on Architecture and Code Optimization (TACO)
ACM Transactions on Computer Systems (TOCS)
Achieving Out-of-Order Performance with Almost In-Order Complexity
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A Trace Cache with DVFS Techniques for a Low Power Microprocessor
ICCIT '08 Proceedings of the 2008 Third International Conference on Convergence and Hybrid Information Technology - Volume 01
| Hi-index | 0.00 |
Energy efficient and performance efficient instruction fetch unit is a critical issue in modern processor design. Trace cache which stores dynamic basic-block stream can significantly improve performance efficiency. Conventional trace cache (CTC) usually adopts set associative structure which requires probing all the data ways in parallel such that only the output of the matched way is used, but the energy for accessing the other ways is wasted. In this paper, we propose a selective way based trace cache (SWTC), which probes only the selected way(s) instead of probing all the data ways. In SWTC, traces are divided into several types and stored into cache by type. Then the trace cache is partially activated and accessed. Based on these design principles, a SWTC model is proposed and evaluated in this paper. Simulation results show that compared to CTC, SWTC can reduce energy consumption on the fetch unit by 20.1% on average, while providing almost the same performance in terms of number of instructions per cycle.