The Design and Evaluation of a Selective Way Based Trace Cache
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
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The trace cache is a solution to achieving high instruction fetches bandwidth by buffering and reusing dynamic instruction traces. This work presents a new trace cache implementation that includes the DVFS (Dynamic Voltage and Frequency Scaling) techniques for energy efficiency. The focus of this paper is to compare the trace cache with DVFS techniques to the conventional trace cache organization where any DVFS technique is not applied.Instead of storing the basic blocks in the unified trace cache space, the first block of each trace is stored in the specific space of the trace cache and the other basic blocks are stored in the rest of the trace cache space. The first basic block area is not voltage scaled because the first basic block should be supplied to processor’s front-end as soon as possible. On the other hand, other basic block area is voltage-scaled down in order to reduce the power consumption. Transistor switching speed of other basic block area is slower than that of the first basic block area due to the lowered supply voltage.Our experiments show that when we adopted the DVFS techniques to the conventional trace cache, 12.8% fetch engine energy consumption is reduced, on average. Applying different supply voltages to each different region of the trace cache, we can reduce the dynamic power consumption. However, we can know that the region which is supplied with lowered voltage inevitably deteriorates the performance of the trace cache by 5.7%.