Energy-aware fetch mechanism: trace cache and BTB customization
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Evaluating trace cache energy efficiency
ACM Transactions on Architecture and Code Optimization (TACO)
The Design and Evaluation of a Selective Way Based Trace Cache
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
| Hi-index | 0.00 |
Power consumption has become an increasing concern inhigh performance microprocessor design in terms of packaging and cooling cost. The fetch unit including instructioncache contributes a large portion of the total power consumption in the microprocessor. The instruction cache itself suffers some hidden power consumption due to dynamic control flows. Although capturing the dynamic control flows toboost performance, conventional trace caches (CTC) may increase power consumption in the fetch unit due to its simultaneous access to both the trace cache and the instructioncache. By avoiding this simultaneous accesses, sequentialtrace caches (STC) achieve lower power consumpt on, butsuffer a significant performance loss at the meantime. In thispaper, we propose dynamic direction prediction based tracecache (DPTC), which avoids simultaneous accesses to thetrace cache and the instruct on cache with the guide of fetchdirection prediction. Experimental results show that dynamicprediction based trace cache can achieve 38.5% power reduction over conventional trace caches and an additional7.2% reduction over STC, on average, while only trading a1.8% performance loss compared to CTC.