Alternative implementations of two-level adaptive branch prediction

Reducing the cost of branches

ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture

Branch folding in the CRISP microprocessor: reducing branch delay to zero

ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture

An evaluation of branch architectures

ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture

Characterization of branch and data dependencies on programs for evaluating pipeline performance

IEEE Transactions on Computers

Checkpoint repair for high-performance out-of-order execution machines

IEEE Transactions on Computers

Reducing the Branch Penalty in Pipelined Processors

Computer

Available instruction-level parallelism for superscalar and superpipelined machines

ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems

Comparing software and hardware schemes for reducing the cost of branches

ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture

Branch history table prediction of moving target branches due to subroutine returns

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture

Single instruction stream parallelism is greater than two

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture

Two-level adaptive training branch prediction

MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture

Optimizing delayed branches

MICRO 15 Proceedings of the 15th annual workshop on Microprogramming

A study of branch prediction strategies

ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture

RISC I: A Reduced Instruction Set VLSI Computer

ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture