Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Analysis of power consumption in memory hierarchies
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
The energy complexity of register files
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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There is an increasing need for obtaining a reasonably accurateestimate of energy dissipation in SoC designs. Arraystructures have a significant contribution to the total systemlevel energy consumption. In this paper, we propose a newmethodology to develop analytical models for accurately estimatingenergy dissipation in array structures. The methodologyis based on the characterization of arrays for energy asa function of micro-architecture level inputs. The coefficientsof the function are extracted using circuit level simulations.We apply the proposed methodology to develop energy modelsfor three different array structures used in the Motorola e5001processor core. The models are validated by comparing themagainst post-layout SPICE simulation. The energy models areseen to be highly accurate with an error margin of less than8%. While the experiments are specific to the e500 processorcore based array structures, the methodology is generic andcan be used to develop energy models for array structures ofany SOC design.