Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Analysis of power consumption in memory hierarchies
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
The energy complexity of register files
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
PASTEL: a parameterized memory characterization system
Proceedings of the conference on Design, automation and test in Europe
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Design and Synthesis of Monotonic Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Analytical models for leakage power estimation of memory array structures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A model-based extensible framework for efficient application design using FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MODEST: a model for energy estimation under spatio-temporal variability
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
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While array structures are a significant source of power dissipation,there is a lack of accurate high-level power estimatorsthat account for varying array circuit implementationstyles. We present a methodology and a tool, the ImplementationDependent Array Power (IDAP) estimator, that modelpower dissipation in SRAM based arrays accurately basedon a high-level description of the array, parameterized bythe array operations, the implementation styles, and varioustechnology dependent parameters. The methodologyis generic and the IDAP tool has been validated on industrialdesigns across a wide variety of array implementationsin the e500 processor core. For these industrial designs,IDAP generates high-level estimates for dynamic power dissipationthat are highly accurate with an error margin ofless than 22.2% of detailed (layout extracted) SPICE simulations.