Validation of an architectural level power analysis technique
DAC '98 Proceedings of the 35th annual Design Automation Conference
The energy complexity of register files
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
A hybrid and adaptive model for predicting register file and SRAM power using a reference design
Proceedings of the 49th Annual Design Automation Conference
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This paper uses a analytical-based characterization model to discuss energy consumption of register files with different circuit techniques that using multi-port SRAM technology. Energy distribution chart of register file with different architectural parameters is acquired according to the calculation results of energy model. How the decoder structure and the dominant component have effect on the power of the register file is demonstrated with emphasise. With this low power method, a 64脳32 bits three-port register file operate at a 500MHz frequency with 54mW power dissipation.