Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Memory modeling for system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Design and Realization of a Low Power Register File Using Energy Model
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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This paper presents a predictive SRAM power model that reduces the changes required to adapt existing models to handle new circuit topologies, process corners, and design space exploration. Analytical equations model the impact of varying common characteristics such as bit-width, entries, segmentation, gating, and sizing while topology specific characteristics are captured empirically from a reference design. On distinct topologies of multi-port read, single- and dual-ended writes, this approach demonstrates an error of 5% and 7% for leakage and dynamic power respectively. We show that for a specific topology, any reference configuration can be used for accurate prediction.