Activity-sensitive architectural power analysis for the control path
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Instruction level power profiling
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Speeding up power estimation of embedded software
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Architecture-level power estimation and design experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework
IEEE Transactions on Computers
Experimental Evaluation of Energy Behavior of Iteration Space Tiling
LCPC '00 Proceedings of the 13th International Workshop on Languages and Compilers for Parallel Computing-Revised Papers
Towards Energy-Aware Iteration Space Tiling
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
A Holistic Approach to System Level Energy Optimization
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Design and Realization of a Low Power Register File Using Energy Model
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks
Proceedings of the conference on Design, automation and test in Europe - Volume 2
End-to-end validation of architectural power models
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Fast and accurate power estimation method based on a PMU counter
Proceedings of the 8th International Conference on Ubiquitous Information Management and Communication
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This paper presents a technique used to do po wer analysis of a real p rocessor at the architectural lev el. The target processor in tegrates a 16-bit DSP an d a 32-bit RISC on a single c hip. O ur po wer estimator pro vides po wer consumption data of the architecture based on the instruction/data flo w stream We demonstrat e the accuracy of the estimator by com paring the po wer valu es it p roduces against measurem en tsm adeby a gate level po wer sim ulator for th e same benc hmark set. Our estimation approac h has been shown to pro vide v ery efficient accurate pow er an alysis at the architectural level.