Power analysis of embedded software: a first step towards software power minimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Activity-sensitive architectural power analysis for the control path
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Validation of an architectural level power analysis technique
DAC '98 Proceedings of the 35th annual Design Automation Conference
System level power analysis
Instruction level power profiling
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
Energy-conscious compilation based on voltage scaling
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
An integrated approach to reducing power dissipation in memory hierarchies
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
A Holistic Approach to System Level Energy Optimization
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
A VLIW low power Java processor for embedded applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Application of Binary Translation to Java Reconfigurable Architectures
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Journal of VLSI Signal Processing Systems
Proceedings of the 42nd annual Design Automation Conference
Compiler-directed high-level energy estimation and optimization
ACM Transactions on Embedded Computing Systems (TECS)
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Algorithmic techniques for memory energy reduction
WEA'03 Proceedings of the 2nd international conference on Experimental and efficient algorithms
Power-Aware scheduling for parallel security processors with analytical models
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
Fast and accurate embedded systems energy characterization using non-intrusive measurements
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Fast and accurate power estimation method based on a PMU counter
Proceedings of the 8th International Conference on Ubiquitous Information Management and Communication
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Architecture-level power estimation has received more attention recently because of its efficiency. This article presents a technique used to do power analysis of processors at the architecture level. It provides cycle-by-cycle power consumption data of the architecture on the basis of the instruction/data flow stream. To characterize the power dissipation of control units, a novel hierarchical method has been developed. Using this technique, a power estimator is implemented for a commercial processor. The accuracy of the estimator is validated by comparing the power values it produces against measurements made by a gate-level power simulator for the same benchmark set. Our estimation approach is shown to provide very efficient and accurate power analysis at the architecture level. The energy models built for first-pass estimation (such as ALU, MAC unit, register files) are reusable for future architecture design modification. In this article, we demonstrate the application of the technique. Furthermore, this technique can evaluate various kinds of software to achieve hardware/software codesign for low power.